SED1354 Datasheet, PDF (125/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 117
15-bpp:
Byte 0
Byte 1
Byte 2
Byte 3
Host Address
5-5-5 RGB
bit 7
bit 0
G₀₂ G₀₁ G₀₀ B₀₄ B₀₃ B₀₂ B₀₁ B₀₀
R₀₄ R₀₃ R₀₂ R₀₁ R₀₀ G₀₄ G₀₃
G₁₂ G₁₁ G₁₀ B₁₄ B₁₃ B₁₂ B₁₁ B₁₀
R₁₄ R₁₃ R₁₂ R₁₁ R₁₀ G₁₄ G₁₃
Display Buffer
P₀P₁P₂ P₃ P₄P₅P₆ P₇
TFT
P_n = (R_n4-0, G_n ^4-0, B_n4-0)
Passive
P_n = (R_n4-1, G_n ^4-1, B_n4-1)
Panel Display
16-bpp:
Byte 0
Byte 1
Byte 2
Byte 3
5-6-5 RGB
bit 7
bit 0
G₀₂ G₀₁ G₀₀ B₀₄ B₀₃ B₀₂ B₀₁ B₀₀
R₀₄ R₀₃ R₀₂ R₀₁ R₀₀ G₀₅ G₀₄ G₀₃
G₁₂ G₁₁ G₁₀ B₁₄ B₁₃ B₁₂ B₁₁ B₁₀
R₁₄ R₁₃ R₁₂ R₁₁ R₁₀ G₁₅ G₁₄ G₁₃
P₀P₁P₂ P₃ P₄ P₅P₆ P₇
TFT
P_n = (R_n4-0, G_n ^5-0, B_n4-0)
Passive
P_n = (R_n4-1, G_n ^5-2, B_n4-1)
Panel Display
Host Address
Display Buffer
Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization
Note
1. The Host-to-Display mapping described here assumes that a Little-Endian interface is
being used.
2. For 8/15/16 bit-per-pixel formats, R_n, G_n, B_n represent the red, green, and blue color
components.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16