SED1354 Datasheet, PDF (49/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 41
Table 7-3: MC68K Bus 2 Interface Timing
Symbol
Parameter
Min
t1
Clock period
30
t2
Clock pulse width high
5
t3
Clock pulse width low
5
t4
A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# = ₄
0, and either UDS#=0 or LDS# = 0
t5
A[20:0], SIZ[1:0], M/R# hold from AS#
0
t6
CS# hold from AS#
0
t7
R/W# setup to DS#
5
t8
R/W# hold from AS#
0
t9¹
AS# = 0 and CS# = 0 to DSACK1# driven high
1
t10
AS# high to DSACK1# high impedance
1
t11
D[31:16] valid to second CLK where CS# = 0 AS# = 0, and
0
either UDS#=0 or LDS# = 0 (write cycle)
t12
D[31:16] hold from falling edge of DSACK1# (write cycle)
0
t13²
Falling edge of UDS# = 0 or LDS# = 0 to D[31:16] driven (read
3
cycle)
t14
D[31:16] valid to DSACK1# falling edge (read cycle)
0
t15
UDS# and LDS# high to D[31:16] invalid/high impedance (read
2
cycle)
t16
AS# high setup to CLK
3
Max Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
ns
ns
ns
ns
11
ns
ns
1. If the SED1354 host interface is disabled, the timing for DSACK1# driven high is relative to
the falling edge of AS# or the first positive edge of CLK after A[20:0] and M/R# become
valid, whichever occurs later.
2. If the SED1354 host interface is disabled, the timing for D[15:0] driven is relative to the falling
edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes valid,
whichever occurs later.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16