SED1354 Datasheet, PDF (70/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 62
7.3.10 FPM-DRAM Self-Refresh Timing
Memory
Clock
RAS#
CAS#
Stopped for
t1
suspend mode
t5
t2
t3
t4
Epson Research and Development
Vancouver Design Center
Restarted for
active mode
Figure 7-16: FPM-DRAM CBR Self-Refresh Timing
Table 7-16: FPM-DRAM CBR Self-Refresh Timing
Symbol
Parameter
Min
Typ
t1
Memory clock
40
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00)
2 t1
t2
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10)
1 t1
CAS# precharge time (REG[22h] bits [3:2] = 00)
2 t1
t3
CAS# precharge time (REG[22h] bits [3:2] = 01 or 10)
1 t1
t4
CAS# setup time (CAS# before RAS# refresh)
0.45 t1 - 2
RAS# precharge time (REG[22h] bits [3:2] = 00)
t5
RAS# precharge time (REG[22h] bits [3:2] = 01 or 10)
2.45 t1 - 1
1.45 t1 - 1
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18