SED1354 Datasheet, PDF (425/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 19
4.4 Register/Memory Mapping
The SED1354 is a memory mapped device. The DRAM on the MPC821 ADS board
extends from address 0h through 3F FFFFh, so the SED1354 must be addressed starting at
40 0000h. A total of 4M bytes of address space is used, where the lower 2M bytes
(from 40 0000h through 5F FFFFh) is reserved for the SED1354 on-chip registers and the
upper 2M bytes (from 60 0000h through 7F FFFFh) is used for the SED1354 display buffer.
4.5 MPC821 Chip Select Configuration
Chip select 4 is used to control the SED1354. The following options are selected in the base
address register (BR4):
• BA[0:16] = 0000 0000 0100 0000 0 – set starting address of SED1354 to 40 0000h.
• AT[0:2] = 0 – ignore address type bits.
• PS[0:1] = 1:0 – memory port size is 16-bit.
• PARE = 0 – disable parity checking.
• WP = 0 – disable write protect.
• MS[0:1] = 0:0 – select General Purpose Chip Select module to control this chip select.
• V = 1 – set valid bit to enable chip select.
The following options were selected in the option register (OR4):
• AM[0:16] = 1111 1111 1100 0000 0 – mask all but upper 10 address bits; SED1354
consumes 4M byte of address space.
• ATM[0:2] = 0 – ignore address type bits.
• CSNT = 0 – normal CS/WE negation.
• ACS[0:1] = 1:1 – delay CS assertion by ½ clock cycle from address lines.
• BI = 1 – assert Burst Inhibit.
• SCY[0:3]= 0 – wait state selection; this field is ignored since external transfer
acknowledge is used; see SETA below.
• SETA = 1 – the SED1354 generates an external transfer acknowledge using the WAIT#
line.
• TRLX = 0 – normal timing.
• EHTR = 0 – normal timing.
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/03/10
SED1354
X19A-G-010-04