SED1354 Datasheet, PDF (85/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4.9 Dual Monochrome 8-Bit Panel Timing
Page 77
FPFRAME
FPLINE
MOD
UD[3:0], LD[3:0]
VDP
VNDP
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241 LINE 2/242
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
1 -1
1 -5
1 -2
1 -6
1 -3
1 -7
1 -4
1 -8
241-1 241-5
241-2 241-6
241-3 241-7
241-4 241-8
HDP
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
HNDP
1-637
1-638
1-639
1-640
241-637
241-638
241-639
241-640
Figure 7-31: Dual Monochrome 8-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16