SED1354 Datasheet, PDF (327/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 3
1 SED1354 Power Consumption
SED1354 power consumption is affected by many system design variables.
• Input clock frequency (CLKI): the CLKI frequency determines the LCD frame-rate, CPU perfor-
mance to memory, and other functions – the higher the input clock frequency, the higher the
frame-rate, performance and power consumption.
• CPU interface: the SED1354 IO V_DD current consumption depends on the BUSCLK frequency,
data width, number of toggling pins, and other factors – the higher the BUSCLK, the higher the
CPU performance and power consumption.
• Core V_DD, IO V_DD voltage levels: the voltage levels of the two independent VDD groups (Core,
IO) affect power consumption – the higher the voltage, the higher the consumption.
• Display mode: the resolution and color depth affect power consumption – the higher the
resolution/color depth, the higher the consumption.
• Internal CLK divide: internal registers allow the input clock to be divided before going to the
internal logic blocks – the higher the divide, the lower the power consumption.
There are two power save modes in the SED1354: Software and Hardware SUSPEND. The power
consumption of these modes is also affected by various system design variables.
• DRAM refresh mode, CBR or self-refresh: self-refresh capable DRAM allows the SED1354 to
disable the internal memory clock thereby saving power.
• CPU bus state during SUSPEND: the state of the CPU bus signals during SUSPEND has a
substantial effect on power consumption. An inactive bus (e.g. BUSCLK = low, Addr = low etc.)
reduces overall system power consumption.
• CLKI state during SUSPEND: disabling the CLKI during SUSPEND has substantial power
savings.
Power Consumption
Issue Date: 98/10/29
SED1354
X19A-G-006-03