SED1354 Datasheet, PDF (148/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 8
Epson Research and Development
Vancouver Design Center
2 Programming the SED1354 Registers
This section describes how to program the SED1354 registers that require special consideration. It
also provides the correct sequence for initializing the SED1354 and disabling the half frame buffer.
For further information on the any of the registers described below, refer to the SED1354 Hardware
Functional Specification, document number X19A-A-002-xx.
2.1 Registers Requiring Special Consideration
2.1.1 REG[01] bit 0 - Memory Type
This bit must not be changed during a DRAM R/W access. Configuring this bit during a DRAM
Refresh will not cause any problems.
Note
This register should be programmed only during initialization and never changed after that.
However, it still must be programmed BEFORE the internal blocks start to R/W the memory (see
Register Initialization in Section 2.1.5).
2.1.2 REG[22] bits 7-2 - Performance Enhancement Register 0
This bit must not be changed during a DRAM R/W access. Configuring this bit during a DRAM
Refresh will not cause any problems.
Note
This register should be programmed only during initialization and never changed after that.
However, it still must be programmed BEFORE the internal blocks start to R/W the memory (see
Register Initialization in Section 2.1.5).
2.1.3 REG[02] bit 1 - Dual/Single Panel Type
This bit must not be changed while the Half Frame Buffer (HFB) is active.
Note
This register should be programmed only during initialization and never changed after that.
However, it still must be programmed BEFORE the HFB starts to R/W the memory (see Register
Initialization in Section 2.1.5).
SED1354
X19A-G-002-06
Programming Notes and Examples
Issue Date: 98/10/28