SED1354 Datasheet, PDF (127/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
11 Clocking
11.1 Maximum MCLK: PCLK Ratios
Page 119
Table 11-1: Maximum PCLK Frequency with EDO-DRAM
Display type
• Single Panel.
• CRT.
• Dual Monochrome/Color Panel with Half Frame Buffer
Disabled.
• Simultaneous CRT + Single Panel.
• Simultaneous CRT + Dual Monochrome/Color Panel
with Half Frame Buffer Disabled.
• Dual Monochrome Panel with Half Frame Buffer
Enabled.
• Simultaneous CRT + Dual Monochrome Panel with
Half Frame Buffer Enable.
• Dual Color Panel with Half Frame Buffer Enabled.
• Simultaneous CRT + Dual Color Panel with Half
Frame Buffer Enable.
N_RC
5, 4, 3
5
4
3
5
4
3
1 bpp
Maximum PCLK Allowed
2 bpp 4 bpp 8 bpp 16 bpp
MCLK
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3
MCLK MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/3
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3
Table 11-2: Maximum PCLK Frequency with FPM-DRAM
Display type
• Single Panel.
• CRT.
• Dual Monochrome/Color Panel with Half Frame Buffer
Disabled.
• Simultaneous CRT + Single Panel.
• Simultaneous CRT + Dual Monochrome/Color Panel
with Half Frame Buffer Disabled.
• Dual Monochrome Panel with Half Frame Buffer
Enabled.
• Simultaneous CRT + Dual Monochrome Panel with
Half Frame Buffer Enable.
• Dual Color Panel with Half Frame Buffer Enabled.
• Simultaneous CRT + Dual Color Panel with Half
Frame Buffer Enable.
N_RC
5, 4, 3
5
4
3
5
4
3
1 bpp
Maximum PCLK allowed
2 bpp 4 bpp 8 bpp 16 bpp
MCLK
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2
MCLK MCLK MCLK MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16