SED1354 Datasheet, PDF (339/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 11
4 Direct Connection to the Philips PR31500/PR31700
4.1 Hardware Description
The SED1354 is easily interfaced to the Philips PR31500/PR31700 processor. In the direct
connection implementation, the SED1354 occupies PC Card slot #1 of the
PR31500/PR31700. Although the address bus of the PR31500/PR31700 is multiplexed, it
can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373). The direct
connection implementation makes use of the Generic MPU host bus interface capability of
the SED1354.
The following diagram demonstrates a typical implementation of the PR31500/PR31700 to
SED1354 interface.
PR31500/PR31700
/RD
/WE
/CARD1CSL
/CARD1CSH
+3.3V
SED1354
IO V_DD, CORE V_DD
RD0#
RD1#
WE0#
WE1#
ALE
A[12:0]
D[31:24]
D[23:16]
/CARD1WAIT
ENDIAN
DCLKOUT
Latch
A23
A[20:13]
System RESET
V_DD
15K pull-up
Clock divider
...or...
See text
Oscillator
CS#
M/R#
RESET#
AB[20:13]
AB[12:0]
DB[7:0]
DB[15:8]
WAIT#
BUSCLK
CLKI
Note:
When connecting the SED1354 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of SED1354 to PR31500/PR31700 Direct Connection
Note
For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 99/03/10
SED1354
X19A-G-005-07