SED1354 Datasheet, PDF (344/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 16
Epson Research and Development
Vancouver Design Center
The Generic MPU host interface control signals of the SED1354 are asynchronous with
respect to the SED1354 bus clock. This gives the system designer full flexibility in
choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether
both clocks should be the same and whether to use DCLKOUT (divided) as the clock
source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum SED1354 clock frequencies.
The SED1354 also has internal clock dividers providing additional flexibility.
SED1354
X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 99/03/10