SED1354 Datasheet, PDF (72/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 64
7.4.2 Suspend Timing
SUSPEND#
Software Suspend
CLKI
LCDPWR
FPFRAME
FPLINE
DRDY
t1
t2
Active
t4
Active
Epson Research and Development
Vancouver Design Center
Note 1
Note 2
Inactive
t5
Inactive
t3
Active
Active
FPSHIFT
FPDAT[15:0]
Memory Access
Active
t6
Allowed
t7
Not Allowed
Active
Allowed
Figure 7-18: LCD Panel Suspend Timing
Table 7-18: LCD Panel Suspend Timing
Symbol
t1
t2
Parameter
LCDPWR inactive to CLKI inactive
SUSPEND# active to FPFRAME, LCDPWR inactive
Min
Typ
Max
128
0
1
t3
First CLKI after SUSPEND# inactive to FPFRAME, LCDPWR
1
active
t4
LCDPWR inactive to FPLINE, FPSHIFT, FPDAT[15:0], DRDY
128
active
t5
First CLKI after SUSPEND# inactive to FPLINE, FPSHIFT,
0
FPDAT[15:0], DRDY active
t6 LCDPWR inactive to Memory Access not allowed
8
t7 _{First CLKI after SUSPEND# inactive to Memory Access allowed}
0
Note
1. t3, t5, and t7 are measured from the first CLKI after SUSPEND# inactive.
2. CLKI may be active throughout SUSPEND# active.
3. Where MCLK is the period of the memory clock.
Units
Frames
Frames
Frames
Frames
Frames
MCLK
MCLK
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18