SED1354 Datasheet, PDF (379/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 9
The following figure illustrates a typical memory read cycle on the MCF5307 system bus.
BCLK0
TS
TA
TIP
A[31:0]
R/W
SIZ[1:0], TT[1:0]
D[31:0]
Transfer Start
Wait States
Transfer
Complete
Sampled when TA low
Next Transfer
Starts
Figure 2-1: MCF5307 Memory Read Cycle
The following figure illustrates a typical memory read cycle on the MCF5307 system bus.
BCLK0
TS
TA
TIP
A[31:0]
R/W
SIZ[1:0], TT[1:0]
D[31:0]
Transfer Start
Valid
Wait States
Transfer
Complete
Next Transfer
Starts
Figure 2-2: MCF5307 Memory Write Cycle
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor
Issue Date: 99/12/23
SED1354
X19A-G-011-06