SED1354 Datasheet, PDF (198/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 58
Epson Research and Development
Vancouver Design Center
** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x06) = 0x00;
/* 0000 0000 */
/*
** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x07) = 0x00;
/* 0000 0000*/
/*
** Registers 8-9: Vertical Display Height (VDP) - 240 lines.
**
240 - 1 = 239t = 0xEF
*/
*(pRegs + 0x08) = 0xEF;
/* 1110 1111 */
*(pRegs + 0x09) = 0x00;
/* 0000 0000 */
/*
** Register A: Vertical Non-Display Period (VNDP)
**
This register must be programed with register 5 (HNDP)
**
to arrive at the frame rate closest to the desired
**
frame rate.
*/
*(pRegs + 0x0A) = 0x01;
/* 0000 0001 */
/*
** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x0B) = 0x00;
/* 0000 0000 */
/*
** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x0C) = 0x00;
/* 0000 0000 */
/*
** Registers E-F: Screen 1 Line Compare - unless setting up for
**
split screen operation use 0x3FF.
*/
*(pRegs + 0x0E) = 0xFF;
/* 1111 1111 */
*(pRegs + 0x0F) = 0x03;
/* 0000 0011 */
/*
** Registers 10-12: Screen 1 Display Start Address - start at the
**
first byte in display memory.
*/
*(pRegs + 0x10) = 0x00;
/* 0000 0000 */
*(pRegs + 0x11) = 0x00;
/* 0000 0000 */
*(pRegs + 0x12) = 0x00;
/* 0000 0000 */
/*
** Register 13-15: Screen 2 Display Start Address - not applicable
**
unless setting up for split screen operation.
*/
*(pRegs + 0x13) = 0x00;
/* 0000 0000 */
*(pRegs + 0x14) = 0x00;
/* 0000 0000 */
*(pRegs + 0x15) = 0x00;
/* 0000 0000 */
/*
SED1354
X19A-G-002-06
Programming Notes and Examples
Issue Date: 98/10/28