SED1354 Datasheet, PDF (84/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 76
Epson Research and Development
Vancouver Design Center
Sync Timing
FPFRAME
FPLINE
Data Timing
MOD
FPLINE
FPSHIFT
UD[7:0]
LD[7:0]
t1
t2
t4
t3
t5
t6
t7
t8
t14
t9
t11 t10
t12 t13
1
2
Figure 7-30: Single Color 16-Bit Panel A.C. Timing
Table 7-24: Single Color 16-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
FPLINE pulse width
MOD delay from FPLINE falling edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
UD[7:0], LD[7:0] setup to FPSHIFT falling edge
UD[7:0], LD[7:0] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
Min
note 2
9
note 3
9
note 4
note 5
note 6
t14 + 3
5
2
2
2
2
18
Typ Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1_min = t3_min - 9Ts
3. t3_min = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
4. t5_min = [((REG[04h] bits [6:0])+1)*8 - 1] Ts
5. t6_min = [(REG[05h] bits [4:0]) + 1)*8 - 25] Ts
6. t7_min = [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18