SED1354 Datasheet, PDF (442/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 12
4 PC Card to SED1354 Interface
Epson Research and Development
Vancouver Design Center
4.1 Hardware Description
The SED1354 is interfaced to the PC Card bus with a minimal amount of glue logic. A PAL
is used to decode the read and write signals of the PC Card bus which generate RD#,
RD/WR#, WE0#, WE1#, and CS# for the SED1354. The PAL also inverts the reset signal
of the PC card since it is active high and the SED1354 uses an active low reset. PAL
equations for this implementation are listed in Section 4.3,“PAL Equations” on page 14.
In this implementation, the address inputs (AB[20:0]) and data bus (DB[15:0] connect
directly to the CPU address (A[20:0]) and data bus (D[15:0]). M/R# is treated as an address
line so that it can be controlled using system address A21. BS# (bus start) is not used and
should be tied low (connected to GND).
The PC Card interface does not provide a bus clock, so one must be supplied for the
SED1354. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI.
The following diagram shows a typical implementation of the PC Card to SED1354
interface.
PC Card
PAL16L8-10
SED1354
OE#
WE#
CE1#
CE2#
RD#
RD/WR#
WE0#
WE1#
REG#
RESET
A[21:0]
D[15:0]
WAIT#
15K pull-up
CS#
RESET#
A21
M/R#
AB[20:0]
DB[15:0]
WAIT#
Oscillator
Note:
When connecting the SED1354 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
BUSCLK
CLKI
Figure 4-1: Typical Implementation of PC Card to SED1354 Interface
Note
For pin mapping see Table 3-1: “Generic MPU Host Bus Interface Pin Mapping”.
SED1354
X19A-G-009-04
Interfacing to the PC Card Bus
Issue Date: 99/03/10