SED1354 Datasheet, PDF (202/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 62
Epson Research and Development
Vancouver Design Center
Table 9-3: TFT Panel
Register
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[06h]
REG[07h]
REG[08h]
REG[09h]
REG[0Ah]
REG[0Bh]
REG[0Ch]
REG[0Dh]
REG[19h]
REG[24h]
REG[26h]
REG[27h]
TFT 16-Bit
Single
640X480@47Hz
Color
0010 0101
0000 0000
0100 1111
0001 0011
0000 0110
0000 0111
1101 1111
0000 0001
0010 1101
0000 0000
0000 0010
0000 1101
0000 0001
0000 0000
load LUT
0000 0000
Notes
set panel type
set MOD rate
set horizontal display width
set horizontal non-display period
set HSYNC start position
set HSYNC polarity and pulse width
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set VSYNC start position
set VSYNC polarity and pulse width
set 8 bpp and LCD enable
set MCLK and PCLK divide
set Look-Up Table address to 0
load Look-Up Table
set Look-Up Table to bank 0
SED1354
X19A-G-002-06
Programming Notes and Examples
Issue Date: 98/10/28