SED1354 Datasheet, PDF (107/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 99
Screen 1 Line Compare Register 0
REG[0Eh]
RW
Screen 1
Screen 1
Screen 1
Screen 1
Screen 1
Screen 1
Screen 1
Screen 1
Line
Line
Line
Line
Line
Line
Line
Line
Compare Bit 7 Compare Bit 6 Compare Bit 5 Compare Bit 4 Compare Bit 3 Compare Bit 2 Compare Bit 1 Compare Bit 0
Screen 1 Line Compare Register 1
REG[0Fh]
RW
Screen 1
Screen 1
n/a
n/a
n/a
n/a
n/a
n/a
Line
Line
Compare Bit 9 Compare Bit 8
REG[0Eh] bits 7-0
REG[0Fh] bits 1-0
Screen 1 Line Compare Bits [9:0]
In split screen mode, the panel is divided into screen 1 and screen 2, with screen 1 above screen 2.
This is the 10-bit value that specifies the screen 1 size in 1-line resolution for split screen mode.
Split screen 1 vertical size in number of lines = (ContentsOfThisRegister) + 1.
Where ContentsOfThisRegister is a 10-bit value comprising of these registers. The maximum
screen 1 vertical size is 1024 lines. Screen 2 is visible only if the screen 1 line compare is less than
the vertical panel size. The starting address for screen 1 is given by the Screen 1 Display Start
Address registers. The starting address for screen 2 is given by the Screen 2 Display Start Address
registers. See Section 10.2, “Image Manipulation” on page 118 and SED1354 Programming Notes
and Examples, document number X19A-G-002-xx, Section 4 for more details.
Note
For normal operation (no split screen) this register must be set greater than the vertical display
height REG[08h] and REG[09h] (e.g. set to 3FFh).
Screen 1 Display Start Address Register 0
REG[10h]
RW
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Screen 1 Display Start Address Register 1
REG[11h]
RW
Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Screen 1 Display Start Address Register 2
REG[12h]
n/a
n/a
n/a
n/a
RW
Start Address Start Address Start Address Start Address
Bit 19
Bit 18
Bit 17
Bit 16
REG[10h] bits 7-0
REG[11h] bits 7-0
REG[12h] bits 3-0
Screen 1 Start Address Bits [19:0]
This register forms the 20-bit address for the starting word of the screen 1 image in the display
buffer. Note that this is a word address. An entry of 0000h into these registers represents the first
word of display memory, an entry of 0001h represents the second word of display memory, and so
on. See Section 10, “Display Configuration” on page 116 for details.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16