SED1354 Datasheet, PDF (91/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4.12 16-Bit TFT Panel Timing
FPFRAME
FPLINE
R[5:1], G[5:0], B[5:1] ^LINE480
DRDY
VNDP
VDP
LINE1
LINE480
FPLINE
FPSHIFT
DRDY
HNDP₁
R[5:1]
G[5:0]
B [5 :1 ]
Note: DRDY is used to indicate the first pixel
Example Timing for 640x480 panel
HDP
HNDP₂
1-1
1-2
1-1
1-2
1-1
1-2
1-640
1-640
1-640
Figure 7-37: 16-Bit TFT Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= HNDP₁ + HNDP₂ = ((REG[05h] bits [4:0]) + 1)*8Ts
Page 83
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16