SED1354 Datasheet, PDF (100/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 92
Epson Research and Development
Vancouver Design Center
8.2.3 Panel/Monitor Configuration Registers
Panel Type Register
REG[02h]
n/a
n/a
Panel Data
Width Bit 1
Panel Data
Width Bit 0
Panel Data Color/Mono
Format Select Panel Select
Dual/Single
Panel Select
RW
TFT/Passive
LCD Panel
Select
bits 5-4
Panel Data Width Bits [1:0]
These bits select passive LCD/TFT panel data width size.
Table 8-3: Panel Data Width Selection
Panel Data Width Bits [1:0]
00
01
10
11
Passive LCD Panel Data
Width Size
4-bit
8-bit
16-bit
Reserved
TFT Panel Data Width Size
9-bit
12-bit
16-bit
Reserved
bit 3
Panel Data Format Select
When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. This bit must be
set to 0 for all other LCD panel formats.
bit 2
Color/Mono Panel Select
When this bit = 1, color passive LCD panel is selected. When this bit = 0, monochrome passive
LCD panel is selected.
bit 1
Dual/Single Panel Select
When this bit = 1, dual passive LCD panel is selected. When this bit = 0, single passive LCD panel
is selected.
Setting this bit for single panel mode should be done only when the Half Frame Buffer is idle. The
Half Frame Buffer is idle during vertical non-display periods or while in suspend mode. For
programming information, see SED1354 Programming Notes and Examples, document number
X19A-G-002-xx.
bit 0
TFT/Passive LCD Panel Select
When this bit = 1, TFT panel is selected. When this bit = 0, passive LCD panel is selected.
MOD Rate Register
REG[03h]
n/a
n/a
MOD Rate
Bit 5
MOD Rate
Bit 4
MOD Rate
Bit 3
MOD Rate
Bit 2
MOD Rate
Bit 1
RW
MOD Rate
Bit 0
bits 5-0
MOD Rate Bits [5:0]
For a non-zero value these bits specify the number of FPLINE between toggles of the MOD output
signal. When these bits are all 0’s the MOD output signal toggles every FPFRAME. These bits are
for passive LCD panels only.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18