SED1354 Datasheet, PDF (117/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 109
bits 3-2
bit 0
Note that for EDO-DRAM and N_RP = 1.5, this bit is automatically forced to 0 to select 2 MCLK for
N_RCD. This is done to satisfy the CAS# address setup time, t_ASC.
The resulting t_RC is related to N_RCD as follows:
t_RC
= (N_RCD) T_M
if EDO and N_RP = 1 or 2
t_RC
= (1.5) T_M
if EDO and N_RP = 1.5
t_RC
= (N_RCD + 0.5) T_M if FPM and N_RP = 1 or 2
t_RC
= (N_RCD) T_M
if FPM and N_RP = 1.5
REG[22h] Bit 4
0
1
Table 8-12: RAS-to-CAS Delay Timing Select
N_RCD
2
1
RAS# to CAS# Delay (t_RCD)
2 T_M
1 T_M
RAS# Precharge Timing (N_RP) Bits [1:0]
Minimum Memory Timing for RAS precharge
These bits select the DRAM RAS# Precharge timing parameter, t_RP. These bits specify the number
(N_RP) of MCLK periods (T_M) used to create t_RP - see the following formulae. Note, these formulae
assume an MCLK duty cycle of 50 +/- 5%.
N_RP
=1
= 1.5
=2
if (t_RP/T_M) < 1
if 1 ≤ (t_RP/T_M) < 1.45
if (t_RP/T_M) ≥ 1.45
The resulting t_RC is related to N_RP as follows:
t_RC
= (N_RP + 0.5) T_M if FPM refresh cycle and N_RP = 1 or 2
t_RC
= (N_RP) T_M
for all other
REG[22h] Bits [3:2]
00
01
10
11
Table 8-13: RAS Precharge Timing Select
N_RP
2
1.5
1
Reserved
RAS# Precharge Width (t_RP)
2 T_M
1.5 T_M
1 T_M
Reserved
Optimal DRAM Timing
The following table contains the optimally programmed values of N_RC, N_RP, and N_RCD for different
DRAM types, at maximum MCLK frequencies.
Table 8-14: Optimal N_RC, N_RP, and N_RCD Values at Maximum MCLK Frequency
DRAM Type ^{DRAM Speed}
T_M
(ns)
(ns)
N_RC
(#MCLK)
N_RP
(#MCLK)
N_RCD
(#MCLK)
50
25
4
1.5
2
EDO
60
30
4
1.5
2
70
33
5
2
2
60
40
4
1.5
2
FPM
70
50
3
1.5
1
Reserved
Must be set to 0.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16