SED1354 Datasheet, PDF (93/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 85
Table 7-28: TFT A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Parameter
FPSHIFT period
FPSHIFT pulse width high
FPSHIFT pulse width low
data setup to FPSHIFT falling edge
data hold from FPSHIFT falling edge
FPLINE cycle time
FPLINE pulse width low
FPFRAME cycle time
FPFRAME pulse width low
horizontal display period
FPLINE setup to FPSHIFT falling edge
Min
Typ
1
0.45
0.45
0.45
0.45
note 2
note 3
note 4
note 5
note 6
0.45
t12
FPFRAME falling edge to FPLINE falling edge
note 7
phase difference
t13
DRDY to FPSHIFT falling edge setup time
0.45
t14
DRDY pulse width
note 8
t15
DRDY falling edge to FPLINE falling edge
note 9
t16
DRDY hold from FPSHIFT falling edge
0.45
t17
FPLINE Falling edge to DRDY active
note 10
Max
Units
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
250
Ts
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t6_min = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts
3. t7_min = [((REG[07h] bits [3:0])+1)*8] Ts
4. t8 _min = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [5:0])+1)] lines
5. t9_min = [((REG[0Ch] bits [2:0])+1)] lines
6. t10_min = [((REG[04h] bits [6:0])+1)*8] Ts
7. t12_min = [((REG[06h] bits [4:0])+1)*8] Ts
8. t14_min = [((REG[04h] bits [6:0])+1)*8] Ts
9. t15_min = [((REG[06h] bits [4:0])+1)*8 - 2] Ts
10. t17_min = [((REG[05h] bits [4:0])+1)*8 - ((REG[06h] bits [4:0])+1)*8 + 2]
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16