 English |
|
|
|
|
|
|
|
| SED1354 Datasheet, PDF (364/472 Pages) Epson Company – Color Graphics LCD/CRT Controller | |||
| |||
| ◁ |
Page 12
4 VR4102 to SED1354 Interface
Epson Research and Development
Vancouver Design Center
4.1 Hardware Description
The NEC VR4102TM microprocessor is specifically designed to support an external LCD
controller by providing the internal address decoding and control signals necessary. By
using this interface only minimal external âglueâ logic is necessary.
The diagram below shows a typical implementation of the VR4102 to SED1354 interface.
NEC VR4102
WR#
SHB#
RD#
LCDCS#
LCDRDY
ADD[25:0]
DAT[15:0]
BUSCLK
Read/Write
Decode Logic
A0
A0
Pull-up
A21
System RESET
SED1354
WE0#
WE1#
RD0#
RD1#
CS#
WAIT#
M/R#
RESET#
AB[20:0]
DB[15:0]
BUSCLK
Notes: The propagation delay of the Read/write Decode Logic shown above must be less than 10 nsec.
When connecting the SED1354 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of VR4102 to SED1354 Interface
Note
For pin mapping see Table 3-1:, âGeneric MPU Host Bus Interface Pin Mappingâ.
SED1354
X19A-G-007-06
Interfacing to the NEC VR4102⢠Microprocessor
Issue Date: 99/03/10
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese