SED1354 Datasheet, PDF (83/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4.8 Single Color 16-Bit Panel Timing
Page 75
FPFRAME
FPLINE
MOD
UD[7:0], LD[7:0]
VDP
VNDP
LINE1 LINE2 LINE3 LINE4
LINE479 LINE480
LINE1 LINE2
FPLINE
MOD
FPSHIFT
UD7
UD6
UD5
UD4
UD3
UD2
UD1
UD0
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
1-R1 1-G6 1-B11
1-B1 1-R7 1-G12
1-G2
1-R3
1-B7 1-R13
1-G8 1-B13
1-B3
1-G4
1-R9 1-G14
1-B9 1-R15
1-R5 1-G10 1-B15
1-B5 1-R11 1-G16
1-G1 1-B6 1-R12
1-R2 1-G7 1-B12
1-B2 1-R8 1-G13
1-G3 1-B8 1-R14
1-R4 1-G9 1-B14
1-B4 1-R10 1-G15
1-G5 1-B10 1-R16
1-R6 1-G11 1-B16
HDP
HNDP
1-G635
1-G636
1-R637
1-B637
1-G638
1-R639
1-B639
1-G640
1-R636
1-B636
1-G637
1-R638
1-B638
1-G639
1-R640
1-B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-29: Single Color 16-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16