SED1354 Datasheet, PDF (41/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 33
Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping
SED1354
Pin Names
FPFRAME
FPLINE
FPSHIFT
DRDY
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
DACRD#
BLANK#
DACP0
DACWR#
DACRS0
DACRS1
HRTC
VRTC
DACCLK
Monochrome Passive
Panel
Single
Dual
4-bit 8-bit 8-bit
MOD
driven 0 D0
LD0
driven 0 D1
LD1
driven 0 D2
LD2
driven 0 D3
LD3
D0
D4
UD0
D1
D5
UD1
D2
D6
UD2
D3
D7
UD3
driven 0 driven 0 driven 0
driven 0 driven 0 driven 0
driven 0 driven 0 driven 0
driven 0 driven 0 driven 0
driven 0 driven 0 driven 0
driven 0 driven 0 driven 0
driven 0 driven 0 driven 0
driven 0 driven 0 driven 0
Color Passive Panel
Single Single
Single
Format 1 Format 2
Dual
4-bit
8-bit
8-bit 8-bit 16-bit
FPFRAME
FPLINE
FPSHIFT
FPSHIFT2
MOD
driven 0 D0
D0
LD0 LD0
driven 0 D1
D1
LD1 LD1
driven 0 D2
D2
LD2 LD2
driven 0 D3
D3
LD3 LD3
D0
D4
D4
UD0 UD0
D1
D5
D5
UD1 UD1
D2
D6
D6
UD2 UD2
D3
D7
D7
UD3 UD3
driven 0 driven 0 driven 0 driven 0 LD4
driven 0 driven 0 driven 0 driven 0 LD5
driven 0 driven 0 driven 0 driven 0 LD6
driven 0 driven 0 driven 0 driven 0 LD7
driven 0 driven 0 driven 0 driven 0 UD4
driven 0 driven 0 driven 0 driven 0 UD5
driven 0 driven 0 driven 0 driven 0 UD6
driven 0
driven 0 driven 0
GPIO4³
GPIO5³
GPIO6³
GPIO7³
GPIO8³
GPIO9³
GPIO10³
GPIO11³
driven 0
UD7
driven 0
Color TFT Panel
CRT
9-bit
R2
R1
R0
G2
G1
G0
B2
B1
B0
12-bit 18-bit¹
DRDY
R3
R5
R2
R4
R1
R3
G3
G5
G2
G4
G1
G3
B3
B5
B2
B4
B1
B3
Note²
Note²
Note²
Note²
Note²
Note²
Note²
Note²
Note²
Note²
Note²
Note²
Note²
driven 0 R0
R2 DACP7
driven 0 driven 0 R1 DACP6
driven 0 G0
G2 DACP5
driven 0 driven 0 G1 DACP4
driven 0 driven 0 G0 DACP3
driven 0 B0
B2 DACP2
driven 0 driven 0 B1 DACP1
DACRD#
BLANK#
DACP0
DACWR#
DACRS0
DACRS1
HRTC
VRTC
DACCLK
Note
1. Although 18-bit TFT panels are supported only 16 data bits (64K colors) are available
- R0 and B0 are not used.
2. If no LCD is active these pins are driven low.
3. All GPIO pins default to input on reset, and unless programmed otherwise should be
connected to either V_SS or IO V_DD if not used.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16