SED1354 Datasheet, PDF (203/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

SED1354F0A Register Summary
X19A-Q-001-03
REG[00h] REVISION CODE REGISTER ²
R0
Product Code
Revision Code
0
0
0
0
0
1
0
0
REG[01h] MEMORY CONFIGURATION REGISTER
n/a¹
Refresh Rate ⁴
Bit 2
Bit 1
Bit 0
1/0
n/a
WE# Control
n/a
RW
FPM/EDO
Memory
REG[02h] PANEL TYPE REGISTER
Panel Data Width ⁵
n/a
n/a
Bit 1
Bit 0
1/0
RW
Panel Data
Format
Select
Color/Mono
Panel Select
Dual/Single
Panel Select
TFT/
Passive
Panel Select
REG[03h] MOD RATE REGISTER
n/a
n/a
Bit 5
Bit 4
MOD Rate
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[04h] HORIZONTAL DISPLAY WIDTH REGISTER
Horizontal Display Width = 8(REG + 1)
n/a
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[05h] HORIZONTAL NON-DISPLAY PERIOD REGISTER
Horizontal Non-Display Period = 8(REG + 1)
n/a
n/a
n/a
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[06h] HRTC/FPLINE START POSITION REGISTER
HRTC/FPLINE Start Position = 8(REG + 1)
n/a
n/a
n/a
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[07h] HRTC/FPLINE PULSE WIDTH REGISTER
HRTC
Polarity
FPLINE
Polarity
n/a
n/a
RW
HRTC/FPLINE Pulse Width = 8(REG + 1)
Bit 3
Bit 2
Bit 1
Bit 0
REG[08h] VERTICAL DISPLAY HEIGHT REGISTER 0
Vertical Display Height = (REG + 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[09h] VERTICAL DISPLAY HEIGHT REGISTER 1
n/a
n/a
n/a
n/a
n/a
RW
Vertical Display Height
n/a
Bit 9
Bit 8
REG[0Ah] VERTICAL NON-DISPLAY PERIOD REGISTER
VNDP
Status (RO)
n/a
Bit 5
Vertical Non-Display Period (VNDP) = (REG + 1)
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[0Bh] VRTC/FPFRAME START POSITION REGISTER
VRTC/FPFRAME Start Position = (REG + 1)
n/a
n/a
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[0Ch] VRTC/FPFRAME PULSE WIDTH REGISTER
VRTC
Polarity
FPFRAME
Polarity
n/a
n/a
n/a
RW
VRTC/FPFRAME Pulse Width = (REG + 1)
Bit 2
Bit 1
Bit 0
REG[0Dh] DISPLAY MODE REGISTER
Simultaneous Display ⁶
n/a
Option Select
Bit 1
Bit 0
Number Of Bits-Per-Pixel ⁷
Bit 2
Bit 1
Bit 0
RW
CRT Enable LCD Enable
REG[0Eh] SCREEN 1 LINE COMPARE REGISTER 0
Screen 1 Line Compare
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[0Fh] SCREEN 1 LINE COMPARE REGISTER 1
RW
Screen 1 Line Compare
n/a
n/a
n/a
n/a
n/a
n/a
Bit 9
Bit 8
REG[11h] SCREEN 1 DISPLAY START ADDRESS REGISTER 1
Screen 1 Display Start Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
RW
Bit 8
REG[12h] SCREEN 1 DISPLAY START ADDRESS REGISTER 2
RW
Screen 1 Display Start Address
n/a
n/a
n/a
n/a
Bit 19
Bit 18
Bit 17
Bit 16
REG[13h] SCREEN 2 DISPLAY START ADDRESS REGISTER 0
Screen 2 Display Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[14h] SCREEN 2 DISPLAY START ADDRESS REGISTER 1
Screen 2 Display Start Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
RW
Bit 8
REG[15h] SCREEN 2 DISPLAY START ADDRESS REGISTER 2
RW
Screen 2 Display Start Address
n/a
n/a
n/a
n/a
Bit 19
Bit 18
Bit 17
Bit 16
REG[16h] MEMORY ADDRESS OFFSET REGISTER 0
Memory Address Offset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[17h] MEMORY ADDRESS OFFSET REGISTER 1
n/a
n/a
n/a
n/a
n/a
RW
Memory Address Offset
n/a
Bit 9
Bit 8
REG[18h] PIXEL PANNING REGISTER
Screen 2 Pixel Panning
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Screen 1 Pixel Panning
Bit 2
Bit 1
RW
Bit 0
REG[19h] CLOCK CONFIGURATION REGISTER
n/a
n/a
n/a
n/a
RW
n/a
MCLK
Divide
PCLK Divide ⁸
Bit 1
Bit 0
REG[1Ah] POWER SAVE CONFIGURATION REGISTER
n/a
n/a
n/a
n/a
LCD Power ^{Suspend Refresh Select 9}
Disable
Bit 1
Bit 0
RW
Software
Suspend
REG[1Bh] MISCELLANIOUS DISABLE REGISTER
RW
Host
Half Frame
Interface
n/a
n/a
n/a
n/a
n/a
n/a
Buffer
Disable
Disable
REG[1Ch] MD CONFIGURATION READBACK REGISTER 0
RO
MD7 Status MD6 Status MD5 Status MD4 Status MD3 Status MD2 Status MD1 Status MD0 Status
REG[1Dh] MD CONFIGURATION READBACK REGISTER 1
MD15
Status
MD14
Status
MD13
Status
MD12
Status
MD11
Status
MD10
Status
MD9
Status
RO
MD8
Status
REG[1Eh] GENERAL IO PINS CONFIGURATION REGISTER 0
GPIO7 Pin GPIO6 Pin GPIO5 Pin GPIO4Pin GPIO3 Pin
IO Config IO Config IO Config IO Config IO Config
GPIO2 Pin
IO Config
GPIO1 Pin
IO Config
RW
GPIO0 Pin
IO Config
REG[1Fh] GENERAL IO PINS CONFIGURATION REGISTER 1
n/a
n/a
n/a
n/a
GPIO11 Pin GPIO10 Pin
IO Config IO Config
GPIO9 Pin
IO Config
RW
GPIO8 Pin
IO Config
REG[20h] GENERAL IO PINS STATUS / CONTROL REGISTER 0
GPIO7 Pin GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin
IO Status IO Status IO Status IO Status IO Status
GPIO2 Pin
IO Status
GPIO1 Pin
IO Status
RW
GPIO0 Pin
IO Status
REG[21h] GENERAL IO PINS STATUS / CONTROL REGISTER 1
GPO Control n/a
n/a
n/a
GPIO11 Pin GPIO10 Pin
IO Status IO Status
GPIO9 Pin
IO Status
RW
GPIO8 Pin
IO Status
REG[22h] PERFORMANCE ENHANCEMENT REGISTER 0
1/0
EDO Read/
Write Delay
RC Timing ¹⁰
Bit 1
Bit 0
RAS# to ^{RAS# Precharge 11 Timing}
CAS# Delay _{Bit 1}
Bit 0
n/a
RW
reserved
REG[23h] PERFORMANCE ENHANCEMENT REGISTER 1
Display FIFO
Disable
n/a
n/a
Bit 4
Display FIFO Threshold
Bit 3
Bit 2
Bit 1
RW
Bit 0
REG[24h] LOOK-UP TABLE ADDRESS REGISTER
RGB Index
n/a
n/a
Bit 1
Bit 0
Bit 3
Look-Up Table Address
Bit 2
Bit 1
RW
Bit 0
REG[26h] LOOK-UP TABLE DATA REGISTER
n/a
n/a
n/a
n/a
Bit 3
Look-Up Table Data
Bit 2
Bit 1
RW
Bit 0
REG[27h] LOOK-UP TABLE BANK SELECT REGISTER
Red Bank Select
n/a
n/a
Bit 1
Bit 0
Blue Bank Select
Bit 1
Bit 0
REG[28h] OR REG[29h] ³ RAMDAC PIXEL READ MASK REGISTER
RAMDAC Data
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
REG[2Ah] OR REG[2Bh] ³ RAMDAC READ MODE ADDRESS REGISTER
RAMDAC Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
REG[2Ch] OR REG[2Dh] ³ RAMDAC WRITE MODE ADDRESS REGISTER
RAMDAC Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
REG[2Eh] OR REG[2Fh] ³ RAMDAC PALETTE DATA REGISTER
RAMDAC Data
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RW
Green Bank Select
Bit 1
Bit 0
RW
Bit 1
Bit 0
RW
Bit 1
Bit 0
RW
Bit 1
Bit 0
RW
Bit 1
Bit 0
Notes
1 n/a bits should be written 0.
reserved bits must be written 0
2 These bits are used to identify the SED1354 at power on / RESET.
3 When using Little-Endian the RAMDAC should be connected to the low byte of the CPU data bus and the lower
register address given used. When using Big-Endian the RAMDAC should be connected to the high byte of the
CPU data bus and the higher register address given used.
4 DRAM Refresh Rate Select
Refresh Rate
Bits [2:0]
000
CLKI Divide Amount
64
Refresh Rate for 33MHz
CLKI
520 kHz
DRAM Refresh
Time/256 cycles
0.5 ms
001
128
010
256
011
512
260 kHz
130 kHz
65 kHz
1 ms
2 ms
4 ms
100
1024
101
2048
33 kHz
16 kHz
8 ms
16 ms
110
111
5 Panel Data Width Selection
4096
8192
8 kHz
4 kHz
32 ms
64 ms
Panel Data Width Bits [1:0]
Passive LCD Panel Data
Width Size
TFT Panel Data Width
Size
00
4-bit
9-bit
01
8-bit
12-bit
10
16-bit
16-bit
11
Reserved
Reserved
REG[10h] SCREEN 1 DISPLAY START ADDRESS REGISTER 0
Screen 1 Display Start Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Page 1
Bit 1
RW
Bit 0
98/09/15