SED1354 Datasheet, PDF (439/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 9
A[25:0]
REG#
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by
driving OE# high and driving the write enable signal (WE#) low. The cycle can be
lengthened by driving WAIT# low for the time needed to complete the cycle.
The figure below illustrates a typical memory read cycle on the PC Card bus.
ADDRESS VALID
CE1#
CE2#
OE#
WAIT#
D[15:0]
A[25:0]
REG#
CE1#
CE2#
OE#
Hi-Z
Transfer Start
DATA VALID
Hi-Z
Transfer Complete
Figure 2-1: PC Card Read Cycle
The figure below illustrates a typical memory write cycle on the PC Card bus.
ADDRESS VALID
WE#
WAIT#
D[15:0]
Hi-Z
Transfer Start
Hi-Z
DATA VALID
Transfer Complete
Figure 2-2: PC Card Write Cycle
Interfacing to the PC Card Bus
Issue Date: 99/03/10
SED1354
X19A-G-009-04