SED1354 Datasheet, PDF (465/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
TX3912
A[12:0]
ENDIAN
D[31:24]
D[23:16]
CARDxWAIT*
DCLKOUT
IT8368E
LHA[20:13],
LHA23
IT8368E
LHA23/MFIO10
LHA22/MFIO9
LHA21/MFIO8
LHA20/MFIO7
LHA19/MFIO6
Page 17
V_{DD pull-up}
Clock divider
SED1354
AB[12:0]
AB[20:13]
System RESET
LHA23
DB[7:0]
DB[15:8]
RESET#
WAIT#
M/R#
...or...
Oscillator
BUSCLK
See text
CLKI
+3.3V
IO V_DD, CORE V_DD
Chip Select
Logic
WE1#
WE0#
RD1#
RD0#
CS#
Notes: The Chip Select Logic shown above is necessary to guarantee the timing parameter t1
of the Generic MPU Host Bus Interface Asynchronous Timing (for details refer to the SED1354 Hardware
Functional Specification, document number X19A-A-002-xx).
When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions
that amy reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes,
or during debug states).
Figure 5-2: SED1354 to TX3912 Connection using Two IT8368E
Note
For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 99/03/10
SED1354
X19A-G-012-03