SED1354 Datasheet, PDF (39/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 31
5.5 Summary of Configuration Options
Pin Name
MD0
MD[3:1]
MD4
MD5
MD[7:6]
MD8
MD9
MD10
MD[15:11]
Table 5-8: Summary of Power On / Reset Options
value on this pin at rising edge of RESET# is used to configure:
1
0
(1/0)
8-bit host bus interface
16-bit host bus interface
Select host bus interface:
000 = SH-3 bus interface
001 = MC68K bus 1 (e.g. MC68000)
010 = MC68K bus 2 (e.g. MC68030)
011 = Generic bus interface (e.g. Philips MIPS PR31500/PR31700; NEC MIPS VR4102)
1XX = reserved
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state)
WAIT# is active low (0 = insert wait state)
Memory Address/GPIO configuration:
00 = symmetrical 256K×16 DRAM. MA[8:0]
01 = symmetrical 1M×16 DRAM. MA[9:0]
10 = asymmetrical 256K×16 DRAM. MA[9:0]
11 = asymmetrical 1M×16 DRAM. MA[11:0]
= DRAM address. MA[11:9]
= DRAM address. MA[11:10]
= DRAM address. MA[11:10]
= DRAM address.
= GPIO[2:1] and GPIO3.
= GPIO[2:1].
= GPIO[2:1].
Configure DACRD#, BLANK#, DACP0, DACWR#,
DACRS0, DACRS1, HRTC, VRTC as General
Purpose IO (GPIO[11:4]).
Configure DACRD#, BLANK#, DACP0, DACWR#,
DACRS0, DACRS1, HRTC, VRTC as DAC and CRT
outputs.
SUSPEND# pin configured as GPO output.
SUSPEND# pin configured as SUSPEND# input.
Active low LCDPWR or GPO polarities.
Active high LCDPWR or GPO polarities.
Not used.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16