SED1354 Datasheet, PDF (366/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 14
Epson Research and Development
Vancouver Design Center
4.3 NEC VR4102™ Configuration
The NEC VR4102™ provides the internal address decoding necessary to map to an external
LCD controller. Physical address 0A00 0000h to 0AFF FFFFh (16M bytes) is reserved for
an external LCD controller.
The SED1354 supports up to 2M bytes of display buffer. The NEC VR4102™ address line
A21 is used to select between the SED1354 display buffer and internal register set.
The VR4102™ uses a read, write and system high-byte enable to interface to an external
LCD controller. The SED1354 uses low and high byte read and write strobes and therefore
minimal “glue” logic is necessary.
SHB#
1
1
0
1
1
0
Table 4-2: NEC/SED1354 Truth Table
NEC Signals
RD#
WR#
0
1
0
1
0
1
1
0
1
0
1
0
Cycle
SED1354 Signals
A0
0
8-bit even address
Read
RD0# = low
RD1# = high
1
8-bit odd address
Read
RD0# = high
RD1# - low
RD0# = low
x
16-bit Read
RD1# - low
0
8-bit even address
Write
WR0# = low
WR1# = high
1
8-bit odd address
Write
WR0# = high
WR1# = low
WR0# = low
x
16-bit Write
WR1# = low
SED1354
X19A-G-007-06
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/03/10