SED1354 Datasheet, PDF (312/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 12
Epson Research and Development
Vancouver Design Center
3 D9000 Specifics
3.1 Interface Signals
The SED1354 is intended for direct connection to most processors, so the FPGA in this environment
simply acts as a pass-through for the required processor interface signals.
Interface
Signals
SED1354 Signal
Name
AB[20:1]
AB0
DB[15:0]
WE1#
M/R#
CS#
BCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
5.0V
3.3V
GND
12.0V
XL
XR
YU
YL
XY
Number of
Signals
19
1
16
1
1
1
1
1
1
1
1
1
1
Table 3-1: Interface Signals
SH-3 Interface
Signal Name
A[20:1]
A0
D[15:0]
WE1#
External Decode
External Decode
CKIO
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Generic CPU
Interface
Signal Name
A[20:1]
A0
D[15:0]
WE#1
External Decode
External Decode
BCLK
nc
RD1#
RD0#
WE0#
WAIT#
RESET#
Comments
Address Bus
Address Bus
Data Bus
Memory / Register Select
SED1354 Chip Select
Bus Clock
Touch Screen
Touch Screen
Touch Screen
Touch Screen
Touch Screen
SDU1354-D9000
X19A-G-003-04
Evaluation Board User Manual
Issue Date: 98/10/29