SED1354 Datasheet, PDF (60/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 52
Epson Research and Development
Vancouver Design Center
Table 7-9: EDO DRAM Read-Write Timing
Symbol
Parameter
Min
Typ
t1
Memory clock period
25
Random read or write cycle time (REG[22h] bits [6:5] = 00)
5 t1
t2
Random read or write cycle time (REG[22h] bits [6:5] = 01)
4 t1
Random read or write cycle time (REG[22h] bits [6:5] = 10)
Row address setup time (REG[22h] bits [3:2] = 00)
t3
Row address setup time (REG[22h] bits [3:2] = 01)
3 t1
2.45 t1
2 t1
Row address setup time (REG[22h] bits [3:2] = 10)
Row address hold time (REG[22h] bits [3:2] = 00 or 10)
t4
Row address hold time (REG[22h] bits [3:2] = 01)
1.45 t1
0.45 t1 - 1
t1 - 1
t5
Column address setup time
0.45 t1 - 1
t6
Column address hold time
RAS# precharge time (REG[22h] bits [3:2] = 00)
0.45 t1 - 1
2 t1 - 1
t7
RAS# precharge time (REG[22h] bits [3:2] = 01)
RAS# precharge time (REG[22h] bits [3:2] = 10)
RAS# to CAS# delay time
(REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10)
t8
RAS# to CAS# delay time
(REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10)
RAS# to CAS# delay time (REG[22h] bits [3:2] = 01)
1.45 t1 - 1
1 t1 - 1
2 t1 - 2
1 t1 - 2
1.45 t1 - 2
t9
Read Data turn-off delay from WE#
0
Write Data delay from WE# (REG[22h] bit 7 = 0)
t10
Write Data delay from WE# (REG[22h] bit 7 = 1)
1.45 t1
0.45 t1
Max
2 t1
1 t1
1.55 t1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18