SED1354 Datasheet, PDF (402/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 14
Epson Research and Development
Vancouver Design Center
MD7
0
0
1
1
MD6
0
1
0
1
Table 4-3: Memory Configuration
Option
1
2
3
4
Memory Selection
Symmetrical 256K x 16 DRAM
Symmetrical 1M x 16 DRAM
Asymmetrical 256K x 16 DRAM
Asymmetrical 1M x 16 DRAM
4.3 MC68328 Chip Select Configuration
In the example interface, chip select CSB3 is used to control the SED1354. A 4M byte
address space is used. The SED1354 control registers are mapped into the bottom half of
this address block, while the display buffer is mapped into the top half. The chip select
should have its RO (Read Only) bit set to 0, and the WAIT field (Wait states) should be set
to 111 to allow the SED1354 to terminate bus cycles externally.
SED1354
X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor
Issue Date: 99/04/19