SED1354 Datasheet, PDF (73/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4.3 Single Monochrome 4-Bit Panel Timing
Page 65
FPFRAME
FPLINE
MOD
UD[3:0], UD[3:0]
VDP
VNDP
LINE1 LINE2 LINE3 LINE4
LINE239 LINE240
LINE1 LINE2
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
1-1 1-5
1-2 1-6
1-3 1-7
1-4 1-8
HDP
HNDP
1-317
1-318
1-319
1-320
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
Figure 7-19: Single Monochrome 4-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16