SED1354 Datasheet, PDF (25/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
4 Block Description
4.1 Functional Block Diagram
16-bit FPM/EDO
DRAM
Register
CPU / MPU
Host
I/F
Memory
Controller
CPU
R/W
Display
FIFO
Power Save
Clocks
Look-Up
Table
LCD
I/F
Bus Clock
Memory Clock
CRTC
Pixel Clock
Page 17
LCD
DAC
Data
DAC
Control
Figure 4-1: System Block Diagram Showing Datapaths
4.2 Functional Block Descriptions
4.2.1 Host Interface
The Host Interface block provides the means for the CPU/MPU to communicate with the display
buffer and internal registers, via one of the supported bus interfaces.
4.2.2 Memory Controller
The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well
as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPM-
DRAM or EDO-DRAM).
4.2.3 Display FIFO
The Display FIFO block fetches display data from the Memory Controller for display refresh.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16