SED1354 Datasheet, PDF (122/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 114
Epson Research and Development
Vancouver Design Center
9 Display Buffer
The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When
CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0] as shown in the following
table.
Table 9-1: SED1354 Addressing
CS#
M/R#
Access
Register access:
0
0
• REG[00h] is addressed when AB[5:0] = 0
• REG[01h] is addressed when AB[5:0] = 1
• REG[n] is addressed when AB[5:0] = n
0
1
Memory access: the 2M byte display buffer is addressed by
AB[20:0]
1
X
SED1354 not selected
The display buffer address space is always 2M bytes. However, the physical display buffer may be
either 512K bytes or 2M bytes. See Section 5.5, “Summary of Configuration Options” on page 31.
The 512K byte display buffer is replicated in the 2M byte address space as shown below.
512K byte Memory
Image Buffer
Half-Frame Buffer
Image Buffer
Half-Frame Buffer
Image Buffer
Half-Frame Buffer
Image Buffer
Half-Frame Buffer
AB[20:0]
000000h
07FFFFh
080000h
0FFFFFh
100000h
17FFFFh
180000h
1FFFFFh
2M byte Memory
Image Buffer
Half-Frame Buffer
Figure 9-1: Display Buffer Addressing
The display buffer will contain an image buffer and may also contain a half-frame buffer.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18