SED1354 Datasheet, PDF (77/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
7.4.5 Single Color 4-Bit Panel Timing
Page 69
FPFRAME
FPLINE
MOD
UD[3:0]
VDP
VNDP
LINE1 LINE2 LINE3 LINE4
LINE479 LINE480
LINE1 LINE2
FPLINE
MOD
FPSHIFT
UD3
UD2
UD1
UD0
1-R1 1-G2 1-B3
1-G1 1-B2 1-R4
1-B1 1-R3 1-G4
1-R2 1-G3 1-B4
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
HDP
HNDP
1-B319
1-R320
1-G320
1-B320
Figure 7-23: Single Color 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
= Vertical Display Period
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
= (REG[0Ah] bits [5:0]) + 1
= ((REG[04h] bits [6:0]) + 1)*8Ts
= ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16