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| SED1354 Datasheet, PDF (44/472 Pages) Epson Company – Color Graphics LCD/CRT Controller | |||
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Page 36
Epson Research and Development
Vancouver Design Center
7 A.C. Characteristics
Conditions:
IO VDD = 2.7V to 5.5V unless otherwise specified
TA = -40° C to 85° C
Trise and Tfall for all inputs must be ⤠5 nsec (10% ~ 90%)
CL = 50pF (Bus / MPU Interface)
CL = 100pF (LCD Panel Interface)
CL = 10pF (Display Buffer Interface)
CL = 10pF (CRT / DAC Interface)
7.1 CPU Interface Timing
7.1.1 SH-3 Interface Timing
t1
t2 t3
CKIO
A[20:0], M/R#
RD/WR#
BS#
CSn#
WEn#
RD#
WAIT#
D[15:0](write)
D[15:0](read)
t4
t6 t7
t8 t12
t9
t11
t13
t5
t10
t12
t14
t15
t16
Figure 7-1: SH-3 Interface Timing
Note
The SH-3 Wait State Control Register for the area in which the SED1354 resides must be set to a
non-zero value.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18
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