SED1354 Datasheet, PDF (174/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 34
Epson Research and Development
Vancouver Design Center
Table 6-2: Related Register Data for CRT Only
Register
REG[04h]
REG[05h]
REG[06h]
REG[07h]
REG[08h]
REG[09h]
REG[0Ah]
REG[0Bh]
REG[0Ch]
REG[0Dh]
REG[19h]
REG[2Ch]
REG[2Eh]
640X480@60Hz 640X480@75Hz 800X600@56Hz 800X600@60Hz
PCLK=25.175MHz PCLK=31.500MHz PCLK=36.0 MHz
PCLK=40.0 MHz
0100 1111 0100 1111 0110 0011 0110 0011
0001 0011 0001 1000 0001 1011 0001 1111
0000 0001 0000 0001 0000 0010 0000 0100
0000 1011 0000 0111 1000 1000 1000 1111
1101 1111 1101 1111 0101 0111 0101 0111
0000 0001 0000 0001 0000 0010 0000 0010
0010 1100 0001 0011 0001 1000 0001 1011
0000 1001 0000 0000 0000 0000 0000 0000
0000 0001 0000 0010 1000 0001 1000 0011
0000 1110 0000 1110 0000 1110 0000 1110
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
Notes
set horizontal display width
set horizontal non-display period
set HSYNC start position
set HSYNC polarity and pulse width
set vertical display height bits 7-0
set vertical display height bits 9-8
set vertical non-display period
set VSYNC start position
set VSYNC polarity and pulse width
set 8 bpp and CRT enable
set MCLK and PCLK divide
set write mode address to 0
load RAMDAC palette data
6.1.2 Simultaneous Display
For Simultaneous Display, only 4/8-bit single passive LCD panels and 9-bit active matrix TFT
panels can be used. Simultaneous Display requires that the panel timing be taken from the CRT
timing registers and thereby limits the number of useful modes supported.
The configuration of both CRT and panel must not violate the limitations as described in “Frame
Rate Calculation” (Chapter 11) of the SED1354 Hardware Functional Specification. For example,
on a 640x480 single panel, the maximum values of both the panel pixel clock and CRT frame rate
are 40 MHz and 85 Hz respectively. When pixel depth is less than 8 bpp, the RAMDAC is
programmed with the same values as the Look-Up Table. The SED1354 does not support Simulta-
neous Display in a color depth greater than 8 bpp.
When color depth is 8 bpp, the RAMDAC should be programmed to mimic the recommended values
in the Look-Up Table as described in Section 3.3.2. The recommendation is that the intensities of
the three prime colors (RGB) be distributed evenly. Table 6-3 shows the recommended RAMDAC
palette data for 8 bpp Simultaneous Display. Table 6-4 shows the related register data for some
possible CRT options with an 8-bit Color 640X480 single passive panel.
SED1354
X19A-G-002-06
Programming Notes and Examples
Issue Date: 98/10/28