SED1354 Datasheet, PDF (129/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 121
Table 11-3: Example Frame Rates
DRAM Type¹
(Speed Grade)
Display
Resolution
Color
Depth
(bpp)
Maximum
Minimum
Pixel
Panel
Clock
(MHz)
HNDP(T_s)
• Single Panel.
• CRT.
800x600^{2 1/2/4/8}
32
16
56
• Dual Mono/Color Panel with Half
Frame Buffer Disabled.⁵
640x480
1/2/4/8
32
• Simultaneous CRT + Single Panel.
16
56
60ns ^{• Simultaneous CRT + Dual}
EDO-DRAM
Mono/Color Panel with Half Frame
Buffer Disabled.⁵
640x240
1/2/4/8
16
33
32
56
1/2/4/8
32
MClk = 33MHz
480x320
N_RC = 4
16
56
N_RP = 1.5
N_RCD = 2
1/2/4/8
32
320x240
16
56
• Dual Color with Half Frame Buffer
Enabled.
800x600^2,3
1/2/4/8
16
16.5
11
32
32
• Dual Mono with Half Frame Buffer
Enabled.
1/2/4/8
16.5
32
640x480
16
11
32
• Single Panel.
• CRT.
800x600^{2 1/2/4/8}
32
16
56
• Dual Mono/Color Panel with Half
Frame Buffer Disabled.⁵
640x480
1/2/4/8
32
• Simultaneous CRT + Single Panel.
16
56
60ns
• Simultaneous CRT + Dual
Mono/Color Panel with Half Frame
Buffer Disabled.⁵
640x240
1/2/4/8
16
1/2/4/8
25
32
56
32
FPM-DRAM
480x320
16
56
MClk = 25MHz
1/2/4/8
32
N_RC = 4
320x240
16
56
N_RP = 1.5
N_RCD = 2
• Dual Mono with Half Frame Buffer 800x600² 1/2/4/8/16
Enabled.
640x480 1/2/4/8/16
12.5
12.5
32
32
640x400 1/2/4/8/16 12.5
32
• Dual Color with Half Frame Buffer
Enabled.
800x600^2,3
1/2/4/8
16
12.5
8.33
32
32
1/2/4/8
12.5
32
640x480
16
8.33
32
Maximum Frame
Rate (Hz)
Panel⁴ CRT
66
55
65
55
101
78
98
78
203
-
200
-
200
-
196
-
388
-
380
-
66
-
43
-
103
-
68
-
50
-
48
-
77
60
75
60
142
-
136
-
152
-
145
-
294
-
280
-
50
-
77
-
92
-
50
-
33
-
77
-
51
-
1. Must set N_RC = 4MCLK. See REG[22h], “Performance Enhancement Register 0”.
2. 800x600 @ 16 bpp requires 2M bytes of display buffer for all display types.
3. 800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame
buffer is enabled.
4. Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too
high for a panel, MCLK should be reduced or PCLK should be divided down.
5. Half Frame Buffer disabled by REG[1Bh] bit 0.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16