SED1354 Datasheet, PDF (32/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 24
Epson Research and Development
Vancouver Design Center
Table 5-1: Host Interface Pin Descriptions (Continued)
Pin Name Type
Pin #
F0A
F1A
F2A
Reset =
Driver _{0 Value}
Description
This pin has multiple functions.
• For SH-3 mode, this pin inputs the write enable signal for the
lower data byte (WE0#).
WE0#
I
8
10
CS
Hi-Z
• For MC68K Bus 1, this pin must be tied to IO V_DD.
• For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic Bus, this pin inputs the write enable signal for the
lower data byte (WE0#).
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
The active polarity of the WAIT# output is configurable on the
rising edge of RESET# - see Section 5.5, “Summary of
Configuration Options” on page 31.
This pin has multiple functions.
• For SH-3 mode, this pin outputs the wait request signal
(WAIT#); MD5 must be pulled low during reset by the internal
pull-down resistor.
• For MC68K Bus 1, this pin outputs the data transfer
WAIT# O
13
15
TS2
Hi-Z
acknowledge signal (DTACK#); MD5 must be pulled high
during reset by an external pull-up resistor.
• For MC68K Bus 2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#); MD5 must be pulled high
during reset by an external pull-up resistor.
• For Generic Bus, this pin outputs the wait signal (WAIT#); MD5
must be pulled low during reset by the internal pull-down
resistor.
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
RESET# I
11
13
CS
Input 0
Active low input to clear all internal registers and to force all
signals to their inactive states.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18