SED1354 Datasheet, PDF (421/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
4 MPC821 to SED1354 Interface
Page 15
4.1 Hardware Description
The interface between the SED1354 and the MPC821 requires no glue logic. All lines are
directly connected. A single resistor is used to speed up the rise time of the WAIT# (TA)
signal when terminating the bus cycle.
BS# (bus start) is not used in this implementation and should be tied low (connected to
GND).
The following diagram shows a typical implementation of the MPC821 to SED1354
interface.
MPC821
A10
A[11:31]
D[0:15]
CS4
TA
WE0
WE1
OE
SYSCLK
Vcc
470
System RESET
SED1354
M/R#
AB[20:0]
DB[15:0]
CS#
WAIT#
WE1#
WE0#
RD1#
RD0#
BUSCLK
RESET#
Note:
When connecting the SED1354 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of MPC821 to SED1354 Interface
Note
For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping” .
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/03/10
SED1354
X19A-G-010-04