SED1354 Datasheet, PDF (365/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 13
4.2 SED1354 Hardware Configuration
The SED1354 uses MD15 through MD0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
SED1354 Hardware Functional Specification, document number X19A-A-002-xx.
The tables below show only those configuration settings important to the PC Card host bus
interface.
.
Table 4-1: Summary of Power-On/Reset Options
SED1354
Pin Name
MD0
MD1
MD2
MD3
MD4
MD5
value on this pin at rising edge of RESET# is used to configure: (1/0)
1
8-bit host bus interface
0
16-bit host bus interface
For host bus interface selection see Table 4-2, “Host Bus Interface Selection”
Little Endian
Big Endian
WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state)
= configuration for NEC VR4102 interface.
MD3
0
0
0
0
1
Table 4-2: Host Bus Interface Selection
MD2
0
0
1
1
x
MD1
0
1
0
1
x
Host Bus Interface
SH-3 bus interface
MC68K bus 1 interface (e.g. MC68000)
MC68K bus 2 interface (e.g. MC68030)
Generic bus interface (e.g. MPC821, ISA bus interface)
Reserved
= configuration for NEC VR4102 interface.
Interfacing to the NEC VR4102™ Microprocessor
Issue Date: 99/03/10
SED1354
X19A-G-007-06