SED1354 Datasheet, PDF (31/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 23
Table 5-1: Host Interface Pin Descriptions (Continued)
Pin Name Type
Pin #
F0A
F1A
F2A
Reset =
Driver _{0 Value}
Description
This pin has multiple functions.
• For SH-3 mode, this pin inputs the write enable signal for the
upper data byte (WE1#).
• For MC68K Bus 1, this pin inputs the upper data strobe
WE1#
I
9
11
CS
Hi-Z
(UDS#).
• For MC68K Bus 2, this pin inputs the data strobe (DS#).
• For Generic Bus, this pin inputs the write enable signal for the
upper data byte (WE1#).
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
This input pin is used to select between the memory and register
address spaces of the SED1354. M/R# is set high to access the
M/R#
I
5
7
C
Hi-Z
memory and low to access the registers. See Section 8.1,
“Register Mapping” on page 90.
CS#
I
BUSCLK I
4
6
C
108 122 C
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
Hi-Z
Chip select input. See Table 5-9: “Host Bus Interface Pin
Mapping,” on page 32.
Hi-Z
System bus clock. See Table 5-9: “Host Bus Interface Pin
Mapping,” on page 32.
This pin has multiple functions.
• For SH-3 mode, this pin inputs the bus start signal (BS#).
• For MC68K Bus 1, this pin inputs the address strobe (AS#).
BS#
I
6
8
CS
Hi-Z
• For MC68K Bus 2, this pin inputs the address strobe (AS#).
• For Generic Bus, this pin must be tied to IO V_DD.
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
RD/WR# I
This pin has multiple functions.
• For SH-3 mode, this pin inputs the RD/WR# signal. The
SED1354 needs this signal for early decode of the bus cycle.
• For MC68K Bus 1, this pin inputs the R/W# signal.
10
12
CS
Hi-Z
• For MC68K Bus 2, this pin inputs the R/W# signal.
• For Generic Bus, this pin inputs the read command for the
upper data byte (RD1#).
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
This pin has multiple functions.
• For SH-3 mode, this pin inputs the read signal (RD#).
• For MC68K Bus 1, this pin must be tied to IO V_DD.
RD#
I
7
9
CS
Hi-Z _{• For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1).}
• For Generic Bus, this pin inputs the read command for the
lower data byte (RD0#).
See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16