SED1354 Datasheet, PDF (291/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 17
6.15 CPU/Bus Interface Header Strips
All of the CPU/Bus interface pins of the SED1354 are connected to the header strips H1 and H2 for
easy interface to a CPU/Bus other than the ISA bus.
Refer to Table 4-1 “CPU/BUS Connector (H1) Pinout,” on page 10 and Table 4-2 “CPU/BUS
Connector (H2) Pinout,” on page 11 for specific settings.
Note
These headers only provide the CPU/Bus interface signals from the SED1354. When another
host bus interface is selected through [MD3:1] configuration, appropriate external decode logic
MUST be used to access the SED1354. See the section “Host Bus Interface Pin Mapping” of the
SED1354 Hardware Functional Specification, document number X19A-A-002-xx.
6.16 Schematic Notes
The following schematics are for reference only and may not reflect actual implementation. Please
request updated information before starting any hardware design.
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/29
SED1354
X19A-G-004-05