SED1354 Datasheet, PDF (383/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
4 MCF5307 To SED1354 Interface
Page 13
4.1 Hardware Connections
The interface between the SED1354 and the MCF5307 requires minimal glue logic. Since
the SED1354 has a single chip select input for both display RAM and registers, a single
external gate is required to produce a negative-OR function of the two MCF5307 chip
selects. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when
terminating the bus cycle.
BS# (bus start) is not used in this implementation and should be tied low (connected GND).
The following diagram shows a typical implementation of the MCF5307 to SED1354
interface.
MCF5307
A21
A[20:0]
D[31:16]
CS4
CS5
TA
WE1
WE0
OE
BCLK0
74AC08 (or equiv.)
Vcc
470
System RESET
SED1354
M/R#
AB[20:0]
DB[15:0]
CS#
WAIT#
WE1#
WE0#
RD1#
RD0#
BUSCLK
RESET#
Note:
When connecting the SED1354 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of MCF5307 to SED1354 Interface
Note
For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping” .
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor
Issue Date: 99/12/23
SED1354
X19A-G-011-06