SED1354 Datasheet, PDF (56/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 48
Epson Research and Development
Vancouver Design Center
Table 7-7: EDO DRAM Read Timing
Symbol
Parameter
t1 Memory clock period
Random read or write cycle time (REG[22h] bits [6:5] = 00)
t2 Random read or write cycle time (REG[22h] bits [6:5] = 01)
Random read or write cycle time (REG[22h] bits [6:5] = 10)
Row address setup time (REG[22h] bits [3:2] = 00)
t3 Row address setup time (REG[22h] bits [3:2] = 01)
Row address setup time (REG[22h] bits [3:2] = 10)
Row address hold time (REG[22h] bits [3:2] = 00 or 10)
t4
Row address hold time (REG[22h] bits [3:2] = 01)
t5 Column address setup time
t6 Column address hold time
t7 CAS# pulse width
t8 CAS# precharge time
t9 RAS# hold time
RAS# precharge time (REG[22h] bits [3:2] = 00)
t10 RAS# precharge time (REG[22h] bits [3:2] = 01)
RAS# precharge time (REG[22h] bits [3:2] = 10)
RAS# to CAS# delay time
(REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10)
t11 RAS# to CAS# delay time
(REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10)
RAS# to CAS# delay time (REG[22h] bits [3:2] = 01)
Access time from RAS#
(REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10)
t12 Access time from RAS#
(REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10)
Access time from RAS# (REG[22h] bits [3:2] = 01)
t13 Access time from CAS#
t14 Access time from CAS# precharge, column address
t15 Read Data hold after CAS# low
t16 Read Data turn-off delay from RAS#
Min
Typ
Max
Units
25
ns
5 t1
ns
4 t1
ns
3 t1
ns
2.45 t1
ns
2 t1
ns
1.45 t1
ns
0.45 t1 - 1
ns
t1 - 1
ns
0.45 t1 - 1
ns
0.45 t1 - 1
ns
0.45 t1
0.55 t1 + 1 ns
0.45 t1 - 1
0.55 t1
ns
1 t1
ns
2 t1 - 1
ns
1.45 t1 - 1
ns
1 t1 - 1
ns
2 t1 - 2
2 t1
ns
1 t1 - 2
1.45 t1 - 2
1 t1
ns
1.55 t1
ns
3 t1 - 11
ns
2 t1 - 11
ns
2.45 t1 - 12 ns
t1 - 10
ns
1.45 t1 - 6 ns
2
ns
2
ns
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18