SED1354 Datasheet, PDF (137/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Epson Research and Development
Vancouver Design Center
Page 129
13.3 Power Save Mode Function Summary
Table 13-1: Power Save Mode Function Summary
Function
Power Save Mode (PSM)
Normal
(Active)
Software
Suspend
Hardware
Suspend
Display Active?
Yes
No
No
Register Access Possible?
Yes
Yes (1)
No
Memory Access Possible?
Yes
No
No
Host Bus Interface Running?
Yes
Yes
No
Memory Interface Running?
Yes
No (2)
No (2)
Note
(1) except for RAMDAC registers.
(2) Yes if CBR suspend mode refresh is selected.
13.4 Pin States in Power Save Modes
Pins
LCD outputs
LCDPWR
DRAM outputs
CRT / DAC outputs
Host Interface outputs
Table 13-2: Pin States in Power Save Modes
Normal
(Active)
Active
On
Active
Active
Active
Pin State
Software
Suspend
Forced Low (1)
Off
Refresh Only (2)
Disabled (3)
Active (4)
Hardware
Suspend
Forced Low (1)
Off
Refresh Only (2)
Disabled (3)
Disabled
Note
1. FPFRAME and FPLINE are forced to their inactive states as defined by REG[0Ch] bit 6
and REG[07h] bit 6 respectively.
2. Selectable: may be CBR refresh, self-refresh or no refresh at all.
3. DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled.
4. Active for non-DAC register access only.
Hardware Functional Specification
Issue Date: 99/05/18
SED1354
X19A-A-002-16