SED1354 Datasheet, PDF (116/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

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Performance Enhancement Register 0
REG[22h]
EDO Read- RC Timing
Write Delay Value Bit 1
RC Timing
Value Bit 0
RAS# to
CAS# Delay
RAS#
Precharge
Timing Bit 1
RAS#
Precharge
Timing Bit 0
n/a
RW
Reserved
Note
Changing this register to non-zero value, or to a different non-zero value, should be done only
when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO
is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For
programming information, see SED1354 Programming Notes and Examples, document number
X19A-G-002-xx.
bit 7
bits 6-5
EDO Read-Write Delay
This bit is used for EDO-DRAM to select the delay during the read-write transition. A “0” selects 2
MCLK delay for the read-write transition. A “1” selects 1 MCLK delay for the read-write DRAM.
This bit has no effect for FPM-DRAM which always uses 1 MCLK delay for the read-write transi-
tion. This bit may be programmed to 1 when the MCLK frequency is less than 30MHz.
RC Timing Value (N_RC) Bits [1:0]
These bits select the DRAM random-cycle timing parameter, t_RC. These bits specify the number
(N_RC) of MCLK periods (T_M) used to create t_RC. N_RC should be chosen to meet t_RC as well as
t_RAS, the RAS pulse width. Use the following two formulae to calculate N_RC then choose the larger
value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
N_RC
= Round-Up (t_RC/T_M)
N_RC
= Round-Up (t_RAS/T_M + N_RP)
= Round-Up (t_RAS/T_M + 1.55)
The resulting t_RC is related to N_RC as follows:
t_RC
= (N_RC) T_M
Table 8-11: Minimum Memory Timing Selection
if N_RP = 1 or 2
if N_RP = 1.5
REG[22h] Bits [6:5]
00
01
10
11
N_RC
5
4
3
Reserved
Minimum Random Cycle
Width (t_RC)
5 T_M
4 T_M
3 T_M
Reserved
bit 4
RAS# to CAS# Delay (N_RCD)
This bit selects the DRAM RAS# to CAS# delay parameter, t_RCD. This bit specifies the number
(N_RCD) of MCLK periods (T_M) used to create t_RCD. N_RCD must be chosen to satisfy the RAS#
access time, t_RAC. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
N_RCD
= Round-Up((t_RAC + 5)/T_M - 1)
=2
= Round-Up(t_RAC/T_M - 1)
= Round-Up(t_RAC/T_M - 0.45)
if EDO and N_RP = 1 or 2
if EDO and N_RP = 1.5
if FPM and N_RP = 1 or 2
if FPM and N_RP = 1.5
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18