SED1354 Datasheet, PDF (444/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 14
Epson Research and Development
Vancouver Design Center
4.3 PAL Equations
The PAL equations used for the implementation presented in this document are as follows.
Note that PALASM syntax uses positive logic. Active low pins are inverted in the pin
declaration section.
CHIP PCCAPP PAL16L8
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
/oe
/we
/ce1
/ce2
/pcreg
breset
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
; bus read enable
; bus write enable
; bus low byte enable
; bus high byte enable
; bus CIS cycle enable
; bus reset (active high)
PIN 12
PIN 13
PIN 14
PIN 15
PIN 16
PIN 17
/we0
/we1
/cs
/rd0
/rd1
/reset
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
COMBINATORIAL
; SED1354 low byte write
; SED1354 high byte write
; SED1354 chip select
; SED1354 low byte read
; SED1354 high byte read
; SED1354 reset
PIN 10
gnd
PIN 20
vcc
; supply
; supply
EQUATIONS
rd0 = oe * ce1 * /pcreg
rd1 = oe * ce2 * /pcreg
we0 = we * ce1 * /pcreg
we1 = we * ce2 * /pcreg
cs = rd0 + rd1 + we0 + we1
reset = breset
; /pcreg means disable in attribute mode
; /pcreg means disable in attribute mode
; /pcreg means disable in attribute mode
; /pcreg means disable in attribute mode
; inversion appears in pin declaration section
4.4 Register/Memory Mapping
The SED1354 is a memory mapped device. The internal registers are mapped in the lower
PC Card memory address space starting at zero. The display buffer requires 2M bytes and
is mapped in the third and fourth megabytes of the PC Card memory address space (ranging
from 200000h to 3fffffh).
The PC Card socket provides 64M bytes of address space. Without further resolution on
the decoding logic (M/R# connected to A21), the entire register set is aliased for every 64
byte boundary within the specified address range above. Since address bits A[25:22] are
ignored, the SED1355 registers and display buffer are aliased 16 times.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
SED1354
X19A-G-009-04
Interfacing to the PC Card Bus
Issue Date: 99/03/10