SED1354 Datasheet, PDF (34/472 Pages) Epson Company – Color Graphics LCD/CRT Controller

Page 26
Epson Research and Development
Vancouver Design Center
Table 5-2: Memory Interface Pin Descriptions (Continued)
Pin Name Type
Pin #
F0A
F1A
F2A
Driver
Reset = 0
Value
Description
MA[8:0] O
43, 41,
39, 37,
35, 34,
36, 38,
40
46, 44,
42, 40,
41, 43,
45, 47,
49
CO1
Output 0 Multiplexed memory address.
This pin has multiple functions.
• For 2M byte DRAM, this is memory address bit 9 (MA9).
• For asymmetrical 512K byte DRAM, this is memory address
MA9
IO 45
51
C/TS1
Hi-Z /
bit 9 (MA9).
Output 0¹ _{• For symmetrical 512K byte DRAM, this pin can be used as}
general purpose IO (GPIO3).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
This pin has multiple functions.
• For asymmetrical 2M byte DRAM, this is memory address bit
10 (MA10).
MA10 IO 42
48
C/TS1
Hi-Z /
Output 0^{1 •}
For symmetrical 2M byte DRAM and all 512K byte DRAM,
this pin can be used as general purpose IO (GPIO1).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
This pin has multiple functions.
• For asymmetrical 2M byte DRAM, this is memory address bit
11 (MA11).
MA11 IO 44
50
C/TS1
Hi-Z /
Output 0^{1 •}
For symmetrical 2M byte DRAM and all 512K byte DRAM,
this pin can be used as general purpose IO (GPIO2).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
1 When configured as IO pins.
SED1354
X19A-A-002-16
Hardware Functional Specification
Issue Date: 99/05/18